The present invention relates in general to depletion mode transistor circuits and, more particularly, to a bias circuit for minimizing quiescent current variation in a depletion mode field effect transistor.
Radio frequency (RF) amplifiers are commonly used in applications such as cellular telephones to amplify high frequency signals in the 800-900 MHz range. The amplified RF signal is transmitted over airways to a receiving unit. A typical RF amplifier includes a metal semiconductor field effect transistor (MESFET) that receives the RF input signal at its gate. The drain of the MESFET is coupled through an RF choke to a positive power supply conductor for providing the amplifier RF output signal.
The gate of the MESFET must be biased for proper operation. The bias point along with the load line and input RF voltage waveform determine the drain current through the power transistor. In order to achieve maximum efficiency, there is a trade-off between maximum transmitted RF power and minimum power consumption. Minimizing power consumption is especially important in battery supplied applications. It is also important to control the bias point over temperature and process variation to maintain constant drain current through the MESFET.
In the prior art, a resistor divider network has been used to bias the power MESFET. The resistors are typically laser trimmed to adjust the bias on each amplifier to compensate for process variation. The resistor trimming is an expensive step in manufacturing and generally fails to compensate for temperature variation in later operation. Another known bias circuit includes complex digital and analog circuitry that samples the drain current of the power transistor and makes dynamic adjustments to the bias voltage. The sampling circuit tends to be over complex and expensive to manufacture.
Hence, a need exists for a simple bias circuit for MESFET circuits to maintain constant drain current.